Wafer-level compliant bump for 3D chip-stacking

Naoya Watanabe; Takeaki Kojima; Tanemasa Asano

doi:10.1109/VTSA.2006.251100

Wafer-level compliant bump for 3D chip-stacking

Naoya Watanabe, Takeaki Kojima, Tanemasa Asano

集積電子システム

研究成果: 書籍/レポートタイプへの寄稿 › 会議への寄与

1 被引用数 (Scopus)

抄録

We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.

本文言語	英語
ホスト出版物のタイトル	2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers
ページ	135-136
ページ数	2
DOI	https://doi.org/10.1109/VTSA.2006.251100
出版ステータス	出版済み - 2006
イベント	2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Hsinchu, 台湾継続期間: 4月 24 2006 → 4月 26 2006

その他

その他	2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA
国/地域	台湾
City	Hsinchu
Period	4/24/06 → 4/26/06

!!!All Science Journal Classification (ASJC) codes

工学（全般）

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10.1109/VTSA.2006.251100

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引用スタイル

Watanabe, N, Kojima, T & Asano, T 2006, Wafer-level compliant bump for 3D chip-stacking. in 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers., 4016636, pp. 135-136, 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA, Hsinchu, 台湾, 4/24/06. https://doi.org/10.1109/VTSA.2006.251100

@inproceedings{fe006b8b81804be18f9018bef34e2fbd,

title = "Wafer-level compliant bump for 3D chip-stacking",

abstract = "We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.",

author = "Naoya Watanabe and Takeaki Kojima and Tanemasa Asano",

year = "2006",

doi = "10.1109/VTSA.2006.251100",

language = "English",

isbn = "142440181X",

pages = "135--136",

booktitle = "2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers",

note = "2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA ; Conference date: 24-04-2006 Through 26-04-2006",

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AU - Watanabe, Naoya

AU - Kojima, Takeaki

AU - Asano, Tanemasa

PY - 2006

Y1 - 2006

N2 - We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.

AB - We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.

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U2 - 10.1109/VTSA.2006.251100

DO - 10.1109/VTSA.2006.251100

M3 - Conference contribution

AN - SCOPUS:34250363151

SN - 142440181X

SN - 9781424401819

SP - 135

EP - 136

BT - 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers

T2 - 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA

Y2 - 24 April 2006 through 26 April 2006

ER -

Wafer-level compliant bump for 3D chip-stacking

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その他

!!!All Science Journal Classification (ASJC) codes

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