抄録
The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and low-power switching characteristics of superconductor devices. Researchers have made tremendous efforts in various aspects, especially in device and circuit design. However, there has been little progress in designing a convincing SFQ-based architectural unit due to a lack of understanding about its potentials and limitations at the architectural level. This article provides the design principles for SFQ-based architectural units with an extremely high-performance neural processing unit (NPU). To achieve our goal, we developed and validated a simulation framework to identify critical architectural bottlenecks in designing a performance-effective SFQ-based NPU. We propose SuperNPU, which outperforms a conventional state-of-the-art NPU by 23 times in terms of computing performance and 1.23 times in power efficiency even with the cooling cost of the 4K environment.
| 本文言語 | 英語 |
|---|---|
| 論文番号 | 9395193 |
| ページ(範囲) | 19-26 |
| ページ数 | 8 |
| ジャーナル | IEEE Micro |
| 巻 | 41 |
| 号 | 3 |
| DOI | |
| 出版ステータス | 出版済み - 5月 1 2021 |
!!!All Science Journal Classification (ASJC) codes
- ソフトウェア
- ハードウェアとアーキテクチャ
- 電子工学および電気工学
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