Sizeenergy tradeoffs for unate circuits computing symmetric Boolean functions

Kei Uchizawa, Eiji Takimoto, Takao Nishizeki

研究成果: ジャーナルへの寄稿学術誌査読

15 被引用数 (Scopus)

抄録

A unate gate is a logical gate computing a unate Boolean function, which is monotone in each variable. Examples of unate gates are AND gates, OR gates, NOT gates, threshold gates, etc. A unate circuit C is a combinatorial logic circuit consisting of unate gates. Let f be a symmetric Boolean function of n variables, such as the Parity function, MOD function, and Majority function. Let m0 and m1 be the maximum numbers of consecutive 0's and consecutive 1's in the value vector of f, respectively, and let l=minm0,m1 and m=maxm0,m1. Let C be a unate circuit computing f. Let s be the size of the circuit C, that is, C consists of s unate gates. Let e be the energy of C, that is, e is the maximum number of gates outputting "1" over all inputs to C. In this paper, we show that there is a tradeoff between the size s and the energy e of C. More precisely, we show that (n+1-l)m≤se. We also present lower bounds on the size s of C represented in terms of n, l and m. Our tradeoff immediately implies that logn≤elogs for every unate circuit C computing the Parity function of n variables.

本文言語英語
ページ(範囲)773-782
ページ数10
ジャーナルTheoretical Computer Science
412
8-10
DOI
出版ステータス出版済み - 3月 4 2011

!!!All Science Journal Classification (ASJC) codes

  • 理論的コンピュータサイエンス
  • コンピュータサイエンス一般

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