Thermal deformation behaviors of electronic packages, stacked-MCP (multi chip package) and SOJ (small outline J-leaded package) were measured by phase-shifting moiré interferometry. This method was developed using a wedged glass plate as a phase shifter to obtain displacement fields with a sensitivity of nanometer scale. Digital image processing was also introduced to determine the strain distributions quantitatively. In stacked-MCP, thermal loading was applied from room temperature 25°C to two elevated temperatures (75 and 100°C), and thermal strains were then examined at these two elevated temperatures. The results showed that the normal strain ε xx concentrated at the ends of two silicon chips, and the transverse strain εxx increased between the two silicon chips. The shear strain γxy increased at the end of the lower silicon chip to 0.30% from 0.17% when the temperature increased by 25°C. In SOJ, the thermal strains were investigated with the two packages before and after mounted on PWB (printed wiring board). The results showed that the strains increased by about 50% when the SOJ was mounted on the PWB.
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