Mechanism of gate voltage spike under digital gate control at IGBT switching operations

This paper reports the mechanism of gate voltage spike in the turn-off operation by a digital gate control. In the previous work, it was clarified that the gate voltage spike V_{g_spike} was generated by parasitic inductance and a large gate current change due to the digital gate control. However, the main cause of resonance leading to V_{g_spike} generation has never been clear. Three types of IGBT modules, which have the same gate inductance and different input capacitance, were tested under three-step digital gate control. It was found that the V_{g_spike} was independent of input capacitance in IGBT. As for the stray capacitance in the digital gate driver, external capacitors C_ex were connected in parallel with the gate driver, and the V_{g_spike} decreased with increasing C_ex. Furthermore, the second vector of the digital control, which was applied for suppressing the overshoot in collector-emitter voltage by a small value, needed to be set as a large value to suppress the V_{g_spike}. From these results, output impedance of gate driver is a key factor for the V_{g_spike}, and the second vector must be optimized for not only the collector voltage overshoot but also V_{g_spike} suppression for safety operation.