Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines

Yosuke Ueno; Yuna Tomida; Teruo Tanimoto; Masamitsu Tanaka; Yutaka Tabuchi; Koji Inoue; Hiroshi Nakamura

doi:10.1109/LCA.2023.3322700

Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines

Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura

先端情報・通信機構学

研究成果: ジャーナルへの寄稿 › 学術誌 › 査読

2 被引用数 (Scopus)

抄録

The bandwidth limit between cryogenic and room-temperature environments is a critical bottleneck in superconducting noisy intermediate-scale quantum computers. This paper presents the first trial of algorithm-aware system-level optimization to solve this issue by targeting the quantum approximate optimization algorithm. Our counter-based cryogenic architecture using single-flux quantum logic shows exponential bandwidth reduction and decreases heat inflow and peripheral power consumption of inter-temperature cables, which contributes to the scalability of superconducting quantum computers.

本文言語	英語
ページ（範囲）	6-9
ページ数	4
ジャーナル	IEEE Computer Architecture Letters
巻	23
号	1
DOI	https://doi.org/10.1109/LCA.2023.3322700
出版ステータス	出版済み - 1月 1 2024

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10.1109/LCA.2023.3322700

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@article{132b9571acfd49959fb5ba28528e8508,

title = "Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines",

abstract = "The bandwidth limit between cryogenic and room-temperature environments is a critical bottleneck in superconducting noisy intermediate-scale quantum computers. This paper presents the first trial of algorithm-aware system-level optimization to solve this issue by targeting the quantum approximate optimization algorithm. Our counter-based cryogenic architecture using single-flux quantum logic shows exponential bandwidth reduction and decreases heat inflow and peripheral power consumption of inter-temperature cables, which contributes to the scalability of superconducting quantum computers.",

author = "Yosuke Ueno and Yuna Tomida and Teruo Tanimoto and Masamitsu Tanaka and Yutaka Tabuchi and Koji Inoue and Hiroshi Nakamura",

note = "Publisher Copyright: {\textcopyright} 2002-2011 IEEE.",

year = "2024",

month = jan,

day = "1",

doi = "10.1109/LCA.2023.3322700",

language = "English",

volume = "23",

pages = "6--9",

journal = "IEEE Computer Architecture Letters",

issn = "1556-6056",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines

AU - Ueno, Yosuke

AU - Tomida, Yuna

AU - Tanimoto, Teruo

AU - Tanaka, Masamitsu

AU - Tabuchi, Yutaka

AU - Inoue, Koji

AU - Nakamura, Hiroshi

PY - 2024/1/1

Y1 - 2024/1/1

N2 - The bandwidth limit between cryogenic and room-temperature environments is a critical bottleneck in superconducting noisy intermediate-scale quantum computers. This paper presents the first trial of algorithm-aware system-level optimization to solve this issue by targeting the quantum approximate optimization algorithm. Our counter-based cryogenic architecture using single-flux quantum logic shows exponential bandwidth reduction and decreases heat inflow and peripheral power consumption of inter-temperature cables, which contributes to the scalability of superconducting quantum computers.

AB - The bandwidth limit between cryogenic and room-temperature environments is a critical bottleneck in superconducting noisy intermediate-scale quantum computers. This paper presents the first trial of algorithm-aware system-level optimization to solve this issue by targeting the quantum approximate optimization algorithm. Our counter-based cryogenic architecture using single-flux quantum logic shows exponential bandwidth reduction and decreases heat inflow and peripheral power consumption of inter-temperature cables, which contributes to the scalability of superconducting quantum computers.

UR - http://www.scopus.com/inward/record.url?scp=85174815071&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85174815071&partnerID=8YFLogxK

U2 - 10.1109/LCA.2023.3322700

DO - 10.1109/LCA.2023.3322700

M3 - Article

AN - SCOPUS:85174815071

SN - 1556-6056

VL - 23

SP - 6

EP - 9

JO - IEEE Computer Architecture Letters

JF - IEEE Computer Architecture Letters

IS - 1

ER -

Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines

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