TY - JOUR
T1 - Electrical properties of poly-Ge on glass substrate grown by two-step solid-phase crystallization
AU - Toko, Kaoru
AU - Nakao, Isakane
AU - Sadoh, Taizoh
AU - Noguchi, Takashi
AU - Miyao, Masanobu
N1 - Funding Information:
The authors are very grateful to Professor H. Nakashima and Dr. D. Wang of Kyushu University for assistance in the Hall measurements. A part of this work was supported by the Grant-in-Aid for Scientific Research from the Ministry of Education, Culture, Sports, Science, and Technology of Japan.
PY - 2009/6
Y1 - 2009/6
N2 - The carrier concentration and mobility of intrinsic holes in poly-Ge films grown by solid-phase crystallization (SPC) were investigated. The two-step SPC method, consisting of low-temperature annealing (425 °C) to obtain large grains and subsequent high-temperature annealing (500 °C) to decrease defects, is proposed. The hole concentration remarkably decreased from 1 × 1018 to 5 × 1017cm-3 with keeping a high-mobility (140 cm2/Vs) after post-annealing.
AB - The carrier concentration and mobility of intrinsic holes in poly-Ge films grown by solid-phase crystallization (SPC) were investigated. The two-step SPC method, consisting of low-temperature annealing (425 °C) to obtain large grains and subsequent high-temperature annealing (500 °C) to decrease defects, is proposed. The hole concentration remarkably decreased from 1 × 1018 to 5 × 1017cm-3 with keeping a high-mobility (140 cm2/Vs) after post-annealing.
UR - https://www.scopus.com/pages/publications/72049094013
UR - https://www.scopus.com/pages/publications/72049094013#tab=citedBy
U2 - 10.1016/j.sse.2009.08.002
DO - 10.1016/j.sse.2009.08.002
M3 - Article
AN - SCOPUS:72049094013
SN - 0038-1101
VL - 53
SP - 1159
EP - 1164
JO - Solid-State Electronics
JF - Solid-State Electronics
IS - 11
ER -