Boolean technology mapping for both ECL and CMOS circuits based on permissible functions and binary decision diagrams

Hitomi Sato, Noboru Takahashi, Yusuke Matsunaga, Masahiro Fujita

研究成果: 書籍/レポート タイプへの寄稿会議への寄与

1 被引用数 (Scopus)

抄録

A Boolean technology mapping with permissible functions is presented. This technique makes use of complementary intermediate logic functions of circuits. Therefore, complementary outputs of ECL gates can be easily handled. High-quality synthesized ECL circuits and CMOS circuits free of logical redundancies are generated. Technology-independent networks are converted into technology-dependent virtual gates network. Virtual gates have an arbitrary number of fan-ins. CMOS virtual networks consist of only NOR and NAND gates, while ECL virtual networks consists of only OR gates (but each gate has complementary outputs). By considering logic function and the device restrictions these virtual gate networks are translated into cell networks using permissible functions.

本文言語英語
ホスト出版物のタイトルProceedings - IEEE International Conference on Computer Design
ホスト出版物のサブタイトルVLSI in Computers and Processors
出版社Publ by IEEE
ページ286-290
ページ数5
ISBN(印刷版)O81862079X
出版ステータス出版済み - 9月 1990
外部発表はい
イベントProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA
継続期間: 9月 17 19909月 19 1990

出版物シリーズ

名前Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

その他

その他Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
CityCambridge, MA, USA
Period9/17/909/19/90

!!!All Science Journal Classification (ASJC) codes

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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