TY - JOUR
T1 - Approximate SFQ-Based Computing Architecture Modeling With Device-Level Guidelines
AU - Mundhe, Pratiksha
AU - Hano, Yuta
AU - Kawakami, Satoshi
AU - Tanimoto, Teruo
AU - Tanaka, Masamitsu
AU - Inoue, Koji
AU - Byun, Ilkwon
N1 - Publisher Copyright:
© 2002-2011 IEEE.
PY - 2025
Y1 - 2025
N2 - Single-flux-quantum (SFQ) logic has emerged as a promising post-Moore technology thanks to its ultra-fast and low-energy operation. However, despite progress in various fields, its feasibility is questionable due to the prohibitive cooling cost. Proven conventional ideas, such as approximate computing, may help to resolve this challenge. However, introducing such ideas has been impossible due to the complex performance, power, and error trade-offs originating from the unique SFQ device characteristics. This work introduces approximate SFQ-based computing (AxSFQ) with an architecture modeling framework and essential design guidelines. Our optimized device-level AxSFQ showcases 30–100 times energy efficiency improvement, which motivates further circuit and architecture-level exploration.
AB - Single-flux-quantum (SFQ) logic has emerged as a promising post-Moore technology thanks to its ultra-fast and low-energy operation. However, despite progress in various fields, its feasibility is questionable due to the prohibitive cooling cost. Proven conventional ideas, such as approximate computing, may help to resolve this challenge. However, introducing such ideas has been impossible due to the complex performance, power, and error trade-offs originating from the unique SFQ device characteristics. This work introduces approximate SFQ-based computing (AxSFQ) with an architecture modeling framework and essential design guidelines. Our optimized device-level AxSFQ showcases 30–100 times energy efficiency improvement, which motivates further circuit and architecture-level exploration.
KW - Single flux quantum (SFQ)
KW - approximate computing
KW - cryogenic computing
KW - modeling
KW - simulation
UR - https://www.scopus.com/pages/publications/105006814511
UR - https://www.scopus.com/pages/publications/105006814511#tab=citedBy
U2 - 10.1109/LCA.2025.3573740
DO - 10.1109/LCA.2025.3573740
M3 - Article
AN - SCOPUS:105006814511
SN - 1556-6056
VL - 24
SP - 253
EP - 256
JO - IEEE Computer Architecture Letters
JF - IEEE Computer Architecture Letters
IS - 2
ER -