Approach of a Coding Conventions for Warning and Suggestion in Transpiler for Rust Convert to RTL

The logic circuit design in Field-Programmable Gate Arrays (FPGA) has few method warnings or suggestions based on coding rules. In our previous work, we implement a transpiler for Rust programming language to convert to Register Transfer Level (RTL). The transpiler is designed to encourage learners of hardware description language (HDL) to design highly readable code. Rust has several warnings and suggestions for coding conventions. However, the transpiler does not cover specific errors of the FPGAs. In this work, we implement warnings and suggestions to promote to learn FPGAs.