A micro-vectorprocessor Architecture - Performance Modeling and Benchmarking -

Takashi Hashimoto, Tetsuo Hironaka, Kazuaki Murakami, Hiroto Yasuura

研究成果: 書籍/レポート タイプへの寄稿会議への寄与

1 被引用数 (Scopus)

抄録

This paper proposes and examines some architectural features suitable for micro-vectorprocessors. Due to the I/O-pin bottleneck, micro-vectorprocessors should save the off-chip memory bandwidth by exploiting the on-chip register bandwidth instead. Those features include the vector-instruction-level multithreading and FIFO vector registers. There are three variations of multithreading: periodic, forced, and round-robin. The paper also formulates the performance of micro-vectorprocessors with such architectural features. And then, the paper evaluates the performance attainable by those micro-vectorprocessors through software simulation. From the benchmark results, it is found that the vector-instruction-level multithreading and FIFO vector registers can improve the performance of the micro-vectorprocessors with the half memory bandwidth comparable to that of ones with the full memory bandwidth. Furthermore, forced multithreading is found to be tolerant to the large memory access latency. From these results, the paper concludes that the forced multithreading at the vector-instruction level is a good candidate for the architectural features suitable to micro-vectorprocessors.

本文言語英語
ホスト出版物のタイトルProceedings of the 7th International Conference on Supercomputing, ICS 1993
出版社Association for Computing Machinery
ページ308-317
ページ数10
ISBN(電子版)089791600X
DOI
出版ステータス出版済み - 8月 1 1993
外部発表はい
イベント7th International Conference on Supercomputing, ICS 1993 - Tokyo, 日本
継続期間: 7月 19 19937月 23 1993

出版物シリーズ

名前Proceedings of the International Conference on Supercomputing
Part F129670

その他

その他7th International Conference on Supercomputing, ICS 1993
国/地域日本
CityTokyo
Period7/19/937/23/93

!!!All Science Journal Classification (ASJC) codes

  • コンピュータサイエンス一般

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