TY - GEN
T1 - A low-glitch and small-logic-area Fibonacci Series DAC
AU - Hokazono, Kazuya
AU - Kanemoto, Daisuke
AU - Pokharel, Ramesh
AU - Tomar, Abhishek
AU - Kanaya, Haruichi
AU - Yoshida, Keiji
PY - 2011/10/13
Y1 - 2011/10/13
N2 - A novel Digital-to-Analog Converter (DAC) utilizing Fibonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The features of the proposed DAC are lower glitch-energy than a binary DAC and the number of logic gates is less than a unary DAC. In the proposed DAC in 0.18μm CMOS process, the glitch-energy of the proposed DAC can be reduced by 75% compared to that of binary DAC, and the number of logic gates can be achieved an around 42% reduction compared to that of the unary DAC. We fabricated a prototype 6-bit Fibonacci Series DAC in order to confirm the operation.
AB - A novel Digital-to-Analog Converter (DAC) utilizing Fibonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The features of the proposed DAC are lower glitch-energy than a binary DAC and the number of logic gates is less than a unary DAC. In the proposed DAC in 0.18μm CMOS process, the glitch-energy of the proposed DAC can be reduced by 75% compared to that of binary DAC, and the number of logic gates can be achieved an around 42% reduction compared to that of the unary DAC. We fabricated a prototype 6-bit Fibonacci Series DAC in order to confirm the operation.
UR - http://www.scopus.com/inward/record.url?scp=80053619404&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80053619404&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2011.6026342
DO - 10.1109/MWSCAS.2011.6026342
M3 - Conference contribution
AN - SCOPUS:80053619404
SN - 9781612848570
T3 - Midwest Symposium on Circuits and Systems
BT - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
T2 - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
Y2 - 7 August 2011 through 10 August 2011
ER -