A design for a low-power digital matched filter applicable to W-CDMA

S. Goto, T. Yamada, N. Takayama, H. Yasuura, Yoshifurni Matsushita, Yasoo Harada

研究成果: 書籍/レポート タイプへの寄稿会議への寄与

8 被引用数 (Scopus)

抄録

This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS) communication system. The proposed architectural approach to reducing the power consumption focuses on the reception registers and the correlation-calculating unit (CCU), which dissipate the majority of the power in a DMF The main features are asynchronous latch clock generation for the reception registers, parallelism of the correlation calculation operations and bit manipulation for chip-correlation operations. A DMF is designed in compliance with the W-CDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-μm CMOS standard cell array technology. The results of the simulations show a power consumption of 9.3 mW (@15.6MHz, 1.6V), which is only about 30% of the power consumption of conventional DMFs.

本文言語英語
ホスト出版物のタイトルProceedings - Euromicro Symposium on Digital System Design
ホスト出版物のサブタイトルArchitectures, Methods and Tools, DSD 2002
編集者Martyn Edwards
出版社Institute of Electrical and Electronics Engineers Inc.
ページ210-217
ページ数8
ISBN(電子版)0769517900, 9780769517902
DOI
出版ステータス出版済み - 2002
外部発表はい
イベントEuromicro Symposium on Digital System Design, DSD 2002 - Dortmund, ドイツ
継続期間: 9月 4 20029月 6 2002

出版物シリーズ

名前Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002

その他

その他Euromicro Symposium on Digital System Design, DSD 2002
国/地域ドイツ
CityDortmund
Period9/4/029/6/02

!!!All Science Journal Classification (ASJC) codes

  • 電子工学および電気工学
  • ハードウェアとアーキテクチャ

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