50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic with Frequency-Increased Clock Distribution
- Ikki Nagaoka
- , Ryota Kashima
- , Masamitsu Tanaka
- , Satoshi Kawakami
- , Teruo Tanimoto
- , Taro Yamashita
- , Koji Inoue
- , Akira Fujimaki
研究成果: ジャーナルへの寄稿 › 学術誌 › 査読
7
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