Variable ordering of binary decision diagrams for multi-level logic minimization

Masahiro Fujita, Yusuke Matsunaga

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


Binary Decision Diagram (BDD) is now widely used in CAD fields, especially in formal verification and logic synthesis. In this paper, variable ordering methods of BDD for the application of multi-level logic minimization are presented. The variable ordering algorithm for sum-of-products representation is based on cover patterns and selects most binary variables first, and the one for multi-level logic representation is based on depth first traversal of circuits. In both cases, the obtained variable orderings are optimized by exchanging a variable with its neighbor in the ordering. Experimental results show the effectiveness of our methods.

Original languageEnglish
Pages (from-to)137-145
Number of pages9
JournalFujitsu Scientific and Technical Journal
Issue number2
Publication statusPublished - Jun 1 1993
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Human-Computer Interaction
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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