Ultralow latency computation based on integrated nanophotonics

Masaya Notomi, Kengo Nozaki, Shota Kita, Akihiko Shinya, Tohru Ishihara, Koji Inoue

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Moore's law for CMOS computers is still continuing, but its near-future saturation is now being discussed. One of the serious saturations is about its latency. The computation delay for a CMOS transistor is already saturated above 10 ps, which will be problematic when ultralow-latency response is required for broad-band data streams, even with parallelization or pipe-line processing. We regard that optical circuits may serve as ultralow-latency computation circuits if they are small enough and tightly combined with electronic circuits. The former requires nanophotonic devices/circuits and the former requires OE/EO conversion with ultrasmall capacitance.

Original languageEnglish
Title of host publicationJSAP-OSA Joint Symposia, JSAP 2018
PublisherOptica Publishing Group (formerly OSA)
ISBN (Print)9784863486942
Publication statusPublished - 2018
EventJSAP-OSA Joint Symposia, JSAP 2018 - Nagoya, Japan
Duration: Sept 18 2018Sept 21 2018

Publication series

NameOptics InfoBase Conference Papers
VolumePart F125-JSAP 2018
ISSN (Electronic)2162-2701


ConferenceJSAP-OSA Joint Symposia, JSAP 2018

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Mechanics of Materials


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