TY - JOUR
T1 - The Effect of Parallel-Connected Varistor on UIS Robustness of SiC MOSFETs for Solid-State Circuit Breakers Application
AU - Lou, Zaiqi
AU - Zhu, Yunjie
AU - Nishizawa, Shin Ichi
AU - Saito, Wataru
N1 - Funding Information:
This work was supported by JSPS Bilateral Joint Research Projects/Seminars JPJSBP120213507 and JST SPRING, Grant Number JPMJSP2136.
Publisher Copyright:
© VDE VERLAG GMBH ∙ Berlin ∙ Offenbach.
PY - 2022
Y1 - 2022
N2 - This paper aims to clarify the effect of parallel-connected varistor on unclamped inductive switching (UIS) robustness of SiC MOSFETs to improve the cut-off current capability of solid-state circuit breakers (SSCB). Because the operation of UIS tests is similar to that in the interruption of SSCB, UIS tests of SiC MOSFETs without varistor and with a parallel-connected varistor were implemented. It was found that the cut-off current of SiC MOSFETs with the varistor is much larger than that of SiC MOSFETs without varistor. The effect of varistor on increase of cut-off current depends on the MOS-gate type. The cut-off current is 3-5 times higher for planar-gate devices and 5-10 times higher for trench-gate devices compared with no varistor condition. To analyze mechanism of cut-off current increased by the varistor, the junction temperature in UIS tests with and without the varistor was estimated by simulation using experimental wave-forms. The simulation results show that the destruction mechanism of SiC MOSFETs is changed by varistor connection due to change of self-heating timing during the UIS.
AB - This paper aims to clarify the effect of parallel-connected varistor on unclamped inductive switching (UIS) robustness of SiC MOSFETs to improve the cut-off current capability of solid-state circuit breakers (SSCB). Because the operation of UIS tests is similar to that in the interruption of SSCB, UIS tests of SiC MOSFETs without varistor and with a parallel-connected varistor were implemented. It was found that the cut-off current of SiC MOSFETs with the varistor is much larger than that of SiC MOSFETs without varistor. The effect of varistor on increase of cut-off current depends on the MOS-gate type. The cut-off current is 3-5 times higher for planar-gate devices and 5-10 times higher for trench-gate devices compared with no varistor condition. To analyze mechanism of cut-off current increased by the varistor, the junction temperature in UIS tests with and without the varistor was estimated by simulation using experimental wave-forms. The simulation results show that the destruction mechanism of SiC MOSFETs is changed by varistor connection due to change of self-heating timing during the UIS.
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M3 - Conference article
AN - SCOPUS:85136106049
SN - 0341-3934
VL - 2022-March
SP - 175
EP - 179
JO - ETG-Fachbericht
JF - ETG-Fachbericht
IS - 165
T2 - 12th International Conference on Integrated Power Electronics Systems, CIPS 2022
Y2 - 15 March 2022 through 17 March 2022
ER -