The architecture of OCMP and its evaluation

K. Saisho, T. Sano, A. Fukuda

Research output: Contribution to conferencePaperpeer-review


By gathering multiple processors in one LSI chip, communication delay between processors becomes shorter and then efficient fine/medium grain parallel processing can be realized. The authors propose a new processor architecture called OCMP (On-Chip Multi-Processing Architecture). OCMP has two characteristics: one is the instruction level dispatching mechanism; and the other is the divided cache system. OCMP employs a fork-join type parallel processing model in order to simplify the dispatching mechanism. By dividing the cache system into shared cache and private cache, the cache coherence problem between processors on the same chip is removed and access conflict on the shared cache is also relaxed. OCMP is evaluated with the instruction level simulator developed by the authors. Two types of instruction level dispatching mechanisms are compared. The memory access mechanism is evaluated with various parameters such as memory access cost, the degree of simultaneous access to shared cache, and so on.

Original languageEnglish
Number of pages7
Publication statusPublished - 1997
Externally publishedYes
Event3rd International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN 1997 - Taipei, Taiwan, Province of China
Duration: Dec 18 1997Dec 20 1997


Other3rd International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN 1997
Country/TerritoryTaiwan, Province of China

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality


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