Systematic design methodology of a wideband multibit continuous-time delta-sigma modulator

Awinash Anand; Nischal Koirala; Ramesh K. Pokharel; Haruichi Kanaya; Keiji Yoshida

doi:10.1155/2013/275289

Systematic design methodology of a wideband multibit continuous-time delta-sigma modulator

Awinash Anand, Nischal Koirala, Ramesh K. Pokharel, Haruichi Kanaya, Keiji Yoshida

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 μm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.

Original language	English
Article number	275289
Journal	International Journal of Microwave Science and Technology
DOIs	https://doi.org/10.1155/2013/275289
Publication status	Published - 2013

All Science Journal Classification (ASJC) codes

Radiation
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1155/2013/275289

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abstract = "Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 μm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.",

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AU - Koirala, Nischal

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AU - Kanaya, Haruichi

AU - Yoshida, Keiji

PY - 2013

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N2 - Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 μm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.

AB - Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 μm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.

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Systematic design methodology of a wideband multibit continuous-time delta-sigma modulator

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