TY - JOUR
T1 - Superconductor Computing for Neural Networks
AU - Ishida, Koki
AU - Byun, Ilkwon
AU - Nagaoka, Ikki
AU - Fukumitsu, Kosuke
AU - Tanaka, Masamitsu
AU - Kawakami, Satoshi
AU - Tanimoto, Teruo
AU - Ono, Takatsugu
AU - Kim, Jangwoo
AU - Inoue, Koji
N1 - Funding Information:
This work was supported in part by the JST-Mirai Program under Grant JPMJMI18E1; in part by JSPS KAKENHI under Grant JP19H01105, Grant JP18H05211, and Grant JP18J21274; and in part by the National Research Foundation of Korea (NRF) under Grant NRF-2019R1A5A1027055 and Grant NRF-2021R1A2C3014131. The circuit was designed with the support by VDEC of the University of Tokyo in collaboration with Cadence Design Systems, Inc., and was fabricated in the CRAVITY of AIST.
Publisher Copyright:
© 1981-2012 IEEE.
PY - 2021/5/1
Y1 - 2021/5/1
N2 - The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and low-power switching characteristics of superconductor devices. Researchers have made tremendous efforts in various aspects, especially in device and circuit design. However, there has been little progress in designing a convincing SFQ-based architectural unit due to a lack of understanding about its potentials and limitations at the architectural level. This article provides the design principles for SFQ-based architectural units with an extremely high-performance neural processing unit (NPU). To achieve our goal, we developed and validated a simulation framework to identify critical architectural bottlenecks in designing a performance-effective SFQ-based NPU. We propose SuperNPU, which outperforms a conventional state-of-the-art NPU by 23 times in terms of computing performance and 1.23 times in power efficiency even with the cooling cost of the 4K environment.
AB - The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and low-power switching characteristics of superconductor devices. Researchers have made tremendous efforts in various aspects, especially in device and circuit design. However, there has been little progress in designing a convincing SFQ-based architectural unit due to a lack of understanding about its potentials and limitations at the architectural level. This article provides the design principles for SFQ-based architectural units with an extremely high-performance neural processing unit (NPU). To achieve our goal, we developed and validated a simulation framework to identify critical architectural bottlenecks in designing a performance-effective SFQ-based NPU. We propose SuperNPU, which outperforms a conventional state-of-the-art NPU by 23 times in terms of computing performance and 1.23 times in power efficiency even with the cooling cost of the 4K environment.
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U2 - 10.1109/MM.2021.3070488
DO - 10.1109/MM.2021.3070488
M3 - Article
AN - SCOPUS:85103891608
SN - 0272-1732
VL - 41
SP - 19
EP - 26
JO - IEEE Micro
JF - IEEE Micro
IS - 3
M1 - 9395193
ER -