Structural and electrical evaluation for strained Si/SiGe on insulator

Dong Wang; Seiichiro Ii; Ken ichi Ikeda; Hideharu Nakashima; Masaharu Ninomiya; Masahiko Nakamae; Hiroshi Nakashima

doi:10.1016/j.tsf.2005.07.338

Structural and electrical evaluation for strained Si/SiGe on insulator

Dong Wang, Seiichiro Ii, Ken ichi Ikeda, Hideharu Nakashima, Masaharu Ninomiya, Masahiko Nakamae, Hiroshi Nakashima

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

Three strained Si/SiGe on insulator wafers having different Ge fractions were evaluated using dual-metal-oxide-semiconductor (dual-MOS) deep level transient spectroscopy (DLTS) and transmission electron microscopy (TEM) methods. The interface of SiGe/buried oxide (BOX) shows roughness less than 1 nm by high resolution TEM observation. The interface states densities (D_it) of SiGe/BOX are approximately 1 × 10¹² cm^{- 2} eV^{- 1}, which is approximately one order of magnitude higher than that of Si/BOX in a Si on insulator wafer measured as reference by the same method of dual-MOS DLTS. The high D_it of SiGe/BOX is not due to interface roughness but due to Ge atoms. The threading dislocations were also clearly observed by TEM and were analyzed.

Original language	English
Pages (from-to)	107-111
Number of pages	5
Journal	Thin Solid Films
Volume	508
Issue number	1-2
DOIs	https://doi.org/10.1016/j.tsf.2005.07.338
Publication status	Published - Jun 5 2006

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Surfaces and Interfaces
Surfaces, Coatings and Films
Metals and Alloys
Materials Chemistry

Access to Document

10.1016/j.tsf.2005.07.338

Cite this

@article{bd3d96c7627242ecb7d347aabd7d036e,

title = "Structural and electrical evaluation for strained Si/SiGe on insulator",

abstract = "Three strained Si/SiGe on insulator wafers having different Ge fractions were evaluated using dual-metal-oxide-semiconductor (dual-MOS) deep level transient spectroscopy (DLTS) and transmission electron microscopy (TEM) methods. The interface of SiGe/buried oxide (BOX) shows roughness less than 1 nm by high resolution TEM observation. The interface states densities (Dit) of SiGe/BOX are approximately 1 × 1012 cm- 2 eV- 1, which is approximately one order of magnitude higher than that of Si/BOX in a Si on insulator wafer measured as reference by the same method of dual-MOS DLTS. The high Dit of SiGe/BOX is not due to interface roughness but due to Ge atoms. The threading dislocations were also clearly observed by TEM and were analyzed.",

author = "Dong Wang and Seiichiro Ii and Ikeda, {Ken ichi} and Hideharu Nakashima and Masaharu Ninomiya and Masahiko Nakamae and Hiroshi Nakashima",

note = "Funding Information: This study was partially supported by a Special Coordination Funds for Promoting Science and Technology from the Ministry of Education, Culture, Sports, Science and Technology of Japan.",

year = "2006",

month = jun,

day = "5",

doi = "10.1016/j.tsf.2005.07.338",

language = "English",

volume = "508",

pages = "107--111",

journal = "Thin Solid Films",

issn = "0040-6090",

publisher = "Elsevier",

number = "1-2",

}

TY - JOUR

T1 - Structural and electrical evaluation for strained Si/SiGe on insulator

AU - Wang, Dong

AU - Ii, Seiichiro

AU - Ikeda, Ken ichi

AU - Nakashima, Hideharu

AU - Ninomiya, Masaharu

AU - Nakamae, Masahiko

AU - Nakashima, Hiroshi

N1 - Funding Information: This study was partially supported by a Special Coordination Funds for Promoting Science and Technology from the Ministry of Education, Culture, Sports, Science and Technology of Japan.

PY - 2006/6/5

Y1 - 2006/6/5

N2 - Three strained Si/SiGe on insulator wafers having different Ge fractions were evaluated using dual-metal-oxide-semiconductor (dual-MOS) deep level transient spectroscopy (DLTS) and transmission electron microscopy (TEM) methods. The interface of SiGe/buried oxide (BOX) shows roughness less than 1 nm by high resolution TEM observation. The interface states densities (Dit) of SiGe/BOX are approximately 1 × 1012 cm- 2 eV- 1, which is approximately one order of magnitude higher than that of Si/BOX in a Si on insulator wafer measured as reference by the same method of dual-MOS DLTS. The high Dit of SiGe/BOX is not due to interface roughness but due to Ge atoms. The threading dislocations were also clearly observed by TEM and were analyzed.

AB - Three strained Si/SiGe on insulator wafers having different Ge fractions were evaluated using dual-metal-oxide-semiconductor (dual-MOS) deep level transient spectroscopy (DLTS) and transmission electron microscopy (TEM) methods. The interface of SiGe/buried oxide (BOX) shows roughness less than 1 nm by high resolution TEM observation. The interface states densities (Dit) of SiGe/BOX are approximately 1 × 1012 cm- 2 eV- 1, which is approximately one order of magnitude higher than that of Si/BOX in a Si on insulator wafer measured as reference by the same method of dual-MOS DLTS. The high Dit of SiGe/BOX is not due to interface roughness but due to Ge atoms. The threading dislocations were also clearly observed by TEM and were analyzed.

UR - http://www.scopus.com/inward/record.url?scp=33646106571&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33646106571&partnerID=8YFLogxK

U2 - 10.1016/j.tsf.2005.07.338

DO - 10.1016/j.tsf.2005.07.338

M3 - Article

AN - SCOPUS:33646106571

SN - 0040-6090

VL - 508

SP - 107

EP - 111

JO - Thin Solid Films

JF - Thin Solid Films

IS - 1-2

ER -

Structural and electrical evaluation for strained Si/SiGe on insulator

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this