Statistical performance-driven module binding in high-level synthesis

Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)


The inevitable fluctuation in fabrication processes results in LSI chips with various critical path delay even though all the chips are fabricated from the same design. Therefore, in LSI design, it is important to estimate what percentage of the fabricated chips will achieve the performance level and to maximize the percentage. This paper presents a model and a method to analyze statistical delay of RT-level data path designs. The method predicts the probability that the fabricated circuits will work at a user specified clock period. Using the method, we can estimate a tight bound on the worst case critical path delay of the circuits. Based on the delay analysis method, a high-level module binding algorithm which maximizes the probability is also proposed. Experimental results demonstrate that the proposed statistical delay analysis method leads to lower cost or higher-performance designs than conventional delay analysis methods.

Original languageEnglish
Title of host publicationProceedings of the 11th International Symposium on System Synthesis, ISSS 1998
EditorsFrancky Catthoor
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)0818686235, 9780818686238
Publication statusPublished - Dec 2 1998
Event11th International Symposium on System Synthesis, ISSS 1998 - Hsinchu, Taiwan, Province of China
Duration: Dec 2 1998Dec 4 1998

Publication series

NameProceedings of the International Symposium on System Synthesis
VolumePart F129250
ISSN (Print)1080-1820


Other11th International Symposium on System Synthesis, ISSS 1998
Country/TerritoryTaiwan, Province of China

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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