Size-constrained code placement for cache miss rate reduction

Hiroyuki Tomiyama, Hiroto Yasuura

Research output: Contribution to journalConference articlepeer-review

7 Citations (Scopus)


In design of an embedded system with a cache, it is important to minimize the cache miss rate to reduce the power consumption as well as to improve the performance of the system. We have previously proposed a code placement method which minimizes miss rates of instruction caches [10], but it makes code size larger. In most cases, code size is a tight design constraint. In this paper, we propose a size-constrained code placement method which minimizes cache miss rates under constraint on code size given by system designers. Experimental results show that the size-constrained code placement method achieves 36% decrease in cache misses with only 1.6% increase in code size compared with a naive placement, while the previous method proposed in [10] decreases 36% of cache misses with 25% increase in code size.

Original languageEnglish
Pages (from-to)96-101
Number of pages6
JournalProceedings of the International Symposium on System Synthesis
Publication statusPublished - Dec 1 1996
EventProceedings of the 1996 9th International Symposium on System Synthesis, ISSS'96 - La Jolla, CA, USA
Duration: Nov 6 1996Nov 8 1996

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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