Routing methodology for minimizing interconnect energy dissipation

In this paper, we propose a new physical design technique for sub-quarter micron system-on-a-chip (SoC). By optimizing the routing grid configuration for the automatic place and route methodology, coupling effects such as crosstalk noise and coupled energy dissipation are almost eliminated with only a small cost to the runtime. Experiments are performed on the design of an image processing circuit using a sub-quarter micron CMOS process with multi-layered interconnects. Simply by employing our proposed technique, net switching energy dissipation can be reduced by about 10% maximum without any area penalty. This significant energy reduction greatly accelerates the performance of SoCs.