Reducing dynamic power and leakage power for embedded systems

Yun Cao; Hiroto Yasuura

doi:10.1109/ASIC.2002.1158073

Reducing dynamic power and leakage power for embedded systems

Yun Cao, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirements, the processors and memories are optimized resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments for several real embedded applications, power reduction without performance penalty is reported range from about 14.5% to 59.2% of dynamic power, and 21.5% to 66.2% of leakage power.

Original language	English
Title of host publication	Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Editors	John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	291-295
Number of pages	5
ISBN (Electronic)	0780374940
DOIs	https://doi.org/10.1109/ASIC.2002.1158073
Publication status	Published - 2002
Externally published	Yes
Event	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: Sept 25 2002 → Sept 28 2002

Publication series

Name	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume	2002-January
ISSN (Print)	1063-0988

Other

Other	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country/Territory	United States
City	Rochester
Period	9/25/02 → 9/28/02

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ASIC.2002.1158073

Cite this

Cao, Y., & Yasuura, H. (2002). Reducing dynamic power and leakage power for embedded systems. In J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (Eds.), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 291-295). Article 1158073 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158073

Reducing dynamic power and leakage power for embedded systems. / Cao, Yun; Yasuura, Hiroto.
Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. ed. / John Chickanosky; Ram K. Krishnamurthy; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. p. 291-295 1158073 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cao, Y & Yasuura, H 2002, Reducing dynamic power and leakage power for embedded systems. in J Chickanosky, RK Krishnamurthy & PR Mukund (eds), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002., 1158073, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 291-295, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, United States, 9/25/02. https://doi.org/10.1109/ASIC.2002.1158073

Cao Y, Yasuura H. Reducing dynamic power and leakage power for embedded systems. In Chickanosky J, Krishnamurthy RK, Mukund PR, editors, Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 291-295. 1158073. (Proceedings of the Annual IEEE International ASIC Conference and Exhibit). doi: 10.1109/ASIC.2002.1158073

Cao, Yun ; Yasuura, Hiroto. / Reducing dynamic power and leakage power for embedded systems. Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. editor / John Chickanosky ; Ram K. Krishnamurthy ; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 291-295 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit).

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AB - This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirements, the processors and memories are optimized resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments for several real embedded applications, power reduction without performance penalty is reported range from about 14.5% to 59.2% of dynamic power, and 21.5% to 66.2% of leakage power.

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Reducing dynamic power and leakage power for embedded systems

Abstract

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