Quantitative evaluation of state-preserving leakage reduction algorithm for L1 data caches

Reiko Komiya, Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become an inevitable issue for high-performance microprocessor designs. Since on-chip caches are major contributors of the leakage, a number of researchers have proposed efficient leakage reduction techniques. However, it is still not clear that 1) what kind of algorithm can be considered and 2) how much they have impact on energy and performance. To answer these questions, we explore runtime cache management algorithm, and evaluate the energy-performance efficiency for several alternatives.

Original languageEnglish
Pages (from-to)862-868
Number of pages7
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number4
Publication statusPublished - 2005

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


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