TY - GEN
T1 - Performance evaluation of a reconfigurable set processor
AU - Mehdipour, Farhad
AU - Noori, Hamid
AU - Honda, Hiroaki
AU - Inoue, Koji
AU - Murakami, Kazuaki
N1 - Copyright:
Copyright 2010 Elsevier B.V., All rights reserved.
PY - 2008
Y1 - 2008
N2 - Performance evaluation is a serious challenge in designing optimizing reconfigurable instruction set processors. A combined and simulation-based model (CAnSO?) is proposed and for performance evaluation of a typical reconfigurable set processor. The proposed model consists of an core that incorporates statistics gathered from cycleaccurate to make a reasonable evaluation. CAnSO has speed advantages and compared to cycle-accurate simulation, proves almost 2% variation in the speedup measurement.
AB - Performance evaluation is a serious challenge in designing optimizing reconfigurable instruction set processors. A combined and simulation-based model (CAnSO?) is proposed and for performance evaluation of a typical reconfigurable set processor. The proposed model consists of an core that incorporates statistics gathered from cycleaccurate to make a reasonable evaluation. CAnSO has speed advantages and compared to cycle-accurate simulation, proves almost 2% variation in the speedup measurement.
UR - http://www.scopus.com/inward/record.url?scp=69949099057&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=69949099057&partnerID=8YFLogxK
U2 - 10.1109/SOCDC.2008.4815603
DO - 10.1109/SOCDC.2008.4815603
M3 - Conference contribution
AN - SCOPUS:69949099057
SN - 9781424425990
T3 - 2008 International SoC Design Conference, ISOCC 2008
SP - I184-I187
BT - 2008 International SoC Design Conference, ISOCC 2008
T2 - 2008 International SoC Design Conference, ISOCC 2008
Y2 - 24 November 2008 through 25 November 2008
ER -