Performance enhancement of partially and fully depleted strained-SOI MOSFETs

Toshinori Numata, Toshifumi Irisawa, Tsutomu Tezuka, Junji Koga, Norio Hirashita, Koji Usuda, Eiji Toyoda, Yoshiji Miyamura, Akihito Tanabe, Naoharu Sugiyama, Shin Ichi Takagi

Research output: Contribution to journalArticlepeer-review

19 Citations (Scopus)


The authors have developed short-channel strained-silicon-on-insulator (strained-SOI) MOSFETs on silicon-germanium (SiGe)-on-insulator (SGOI) substrates fabricated by the Ge condensation technique. 35-nm-gate-length strained-SOI MOSFETs were successfully fabricated. The strain in Si channel is still maintained for the gate length of 35 nm. The performance enhancement of over 15% was obtained in 70-nm-gate-length strained-SOI n-MOSFETs. Fully depleted strained-SOI MOSFETs with back gate were successfully fabricated on SGOI substrate with SiGe layers as thin as 25 nm. The back-gate bias control successfully operated and the higher current drive was obtained by a combination of the low doping channel and the back-gate control.

Original languageEnglish
Pages (from-to)1030-1038
Number of pages9
JournalIEEE Transactions on Electron Devices
Issue number5
Publication statusPublished - May 2006
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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