OTFT device modeling with Verilog-A language including non-linear effects of source/drain contact resistance

Gordon Yip; Shintarou Sugimoto; Reiji Hattori

OTFT device modeling with Verilog-A language including non-linear effects of source/drain contact resistance

Gordon Yip, Shintarou Sugimoto, Reiji Hattori

Research output: Contribution to journal › Article › peer-review

Abstract

A device model for Organic Thin-Film Transistors (OTFT) written in Verilog-A, a high-level analog hardware description language (AHDL), is presented. The non-linear contact resistance with respect to gate or drain bias voltage due to Schottky-barrier narrowing at source/drain contacts has been successfully integrated into this model.

Original language	English
Pages (from-to)	S102-S106
Journal	Journal of the Korean Physical Society
Volume	48
Issue number	SUPPL. 1
Publication status	Published - Jan 2006

All Science Journal Classification (ASJC) codes

Physics and Astronomy(all)

Cite this

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title = "OTFT device modeling with Verilog-A language including non-linear effects of source/drain contact resistance",

abstract = "A device model for Organic Thin-Film Transistors (OTFT) written in Verilog-A, a high-level analog hardware description language (AHDL), is presented. The non-linear contact resistance with respect to gate or drain bias voltage due to Schottky-barrier narrowing at source/drain contacts has been successfully integrated into this model.",

author = "Gordon Yip and Shintarou Sugimoto and Reiji Hattori",

year = "2006",

month = jan,

language = "English",

volume = "48",

pages = "S102--S106",

journal = "Journal of the Korean Physical Society",

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publisher = "Korean Physical Society",

number = "SUPPL. 1",

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AU - Yip, Gordon

AU - Sugimoto, Shintarou

AU - Hattori, Reiji

PY - 2006/1

Y1 - 2006/1

N2 - A device model for Organic Thin-Film Transistors (OTFT) written in Verilog-A, a high-level analog hardware description language (AHDL), is presented. The non-linear contact resistance with respect to gate or drain bias voltage due to Schottky-barrier narrowing at source/drain contacts has been successfully integrated into this model.

AB - A device model for Organic Thin-Film Transistors (OTFT) written in Verilog-A, a high-level analog hardware description language (AHDL), is presented. The non-linear contact resistance with respect to gate or drain bias voltage due to Schottky-barrier narrowing at source/drain contacts has been successfully integrated into this model.

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SP - S102-S106

JO - Journal of the Korean Physical Society

JF - Journal of the Korean Physical Society

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ER -

OTFT device modeling with Verilog-A language including non-linear effects of source/drain contact resistance

Abstract

All Science Journal Classification (ASJC) codes

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