TY - GEN
T1 - Optimal intermediate bus capacitance for system stability on distributed power architecture
AU - Abe, Seiya
AU - Hirokawa, Masahiko
AU - Shoyama, Masahito
AU - Ninomiya, Tamotsu
PY - 2008/9/29
Y1 - 2008/9/29
N2 - The power supply system which requires the low-voltage / high-current output has been changing from conventional centralized power system to distributed power system. The distributed power system consists of bus converter and POL. The most important factor is the system stability in bus architecture design. The overlap between the output impedance of bus converter and input impedance of POL causes system instability, and it has been an actual problem. Increasing the bus capacitor, system stability can be reduced easily. However, due to the limited space on the system board, increasing of bus capacitors is impractical. The urgent solution of the issue is desired strongly. This paper presents the output impedance design for on-board distributed power system by means of full-regulated bus converter. The output impedance peak of the bus converter and the input impedance of the POL are analyzed, and it is conformed by experimentally for stability criterion. Furthermore, the optimal intermediate bus capacitance design for system stability is proposed.
AB - The power supply system which requires the low-voltage / high-current output has been changing from conventional centralized power system to distributed power system. The distributed power system consists of bus converter and POL. The most important factor is the system stability in bus architecture design. The overlap between the output impedance of bus converter and input impedance of POL causes system instability, and it has been an actual problem. Increasing the bus capacitor, system stability can be reduced easily. However, due to the limited space on the system board, increasing of bus capacitors is impractical. The urgent solution of the issue is desired strongly. This paper presents the output impedance design for on-board distributed power system by means of full-regulated bus converter. The output impedance peak of the bus converter and the input impedance of the POL are analyzed, and it is conformed by experimentally for stability criterion. Furthermore, the optimal intermediate bus capacitance design for system stability is proposed.
UR - http://www.scopus.com/inward/record.url?scp=52349098519&partnerID=8YFLogxK
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U2 - 10.1109/PESC.2008.4591997
DO - 10.1109/PESC.2008.4591997
M3 - Conference contribution
AN - SCOPUS:52349098519
SN - 9781424416684
T3 - PESC Record - IEEE Annual Power Electronics Specialists Conference
SP - 611
EP - 616
BT - PESC '08 - 39th IEEE Annual Power Electronics Specialists Conference - Proceedings
T2 - PESC '08 - 39th IEEE Annual Power Electronics Specialists Conference
Y2 - 15 June 2008 through 19 June 2008
ER -