TY - GEN
T1 - On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
AU - Fujita, Masahiro
AU - Matsunaga, Yusuke
AU - Kakuda, Taeko
PY - 1992
Y1 - 1992
N2 - We have developed multi-level logic minimization programs using Binary Decision Diagram (BDD). Here we present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circuits is based on depth first traverse of circuits. In both cases, the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering.
AB - We have developed multi-level logic minimization programs using Binary Decision Diagram (BDD). Here we present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circuits is based on depth first traverse of circuits. In both cases, the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering.
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M3 - Conference contribution
AN - SCOPUS:0027047925
SN - 0818626453
T3 - Proc Eur Conf Des Autom
SP - 50
EP - 54
BT - Proc Eur Conf Des Autom
PB - Publ by IEEE
T2 - Proceedings the European Conference on Design Automation
Y2 - 16 March 1992 through 19 March 1992
ER -