Omitting cache look-up for high-performance, low-power microprocessors

Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami

Research output: Contribution to journalArticlepeer-review


In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache". The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.

Original languageEnglish
Pages (from-to)279-287
Number of pages9
JournalIEICE Transactions on Electronics
Issue number2
Publication statusPublished - Feb 2002
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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