Nano-lithography free formation of high density Ge-on-insulator network for epitaxial template

Hiroyuki Yokoyama; Kaoru Toko; Taizoh Sadoh; Masanobu Miyao

doi:10.1063/1.3691258

Nano-lithography free formation of high density Ge-on-insulator network for epitaxial template

Hiroyuki Yokoyama, Kaoru Toko, Taizoh Sadoh, Masanobu Miyao

Electronic Devices

Research output: Contribution to journal › Article › peer-review

10 Citations (Scopus)

Abstract

High-quality Ge-on-insulator (GOI) structures are essential for integrating multi-functional devices onto the Si-platform. We develop the nano-lithography free method for single-crystalline GOI networks by combining partial Ge evaporation and rapid-melting growth techniques. This realizes chip size GOI with high Ge coverage fractions (>75), which is crisscrossed with nano-spacing (∼100 nm width). Over-epitaxy of Ge on the GOI network is also examined, which achieves single-crystalline GOI uniform-plane by covering the nano-spacing. This proves the validity of high-density GOI networks as the epitaxial template. This method will facilitate the heterogeneous integration of Ge, III-V semiconductors, and magnetic materials on the Si-platform.

Original language	English
Article number	092111
Journal	Applied Physics Letters
Volume	100
Issue number	9
DOIs	https://doi.org/10.1063/1.3691258
Publication status	Published - Feb 27 2012

All Science Journal Classification (ASJC) codes

Physics and Astronomy (miscellaneous)

Access to Document

10.1063/1.3691258

Cite this

@article{0ddf8fa748634bdbbe92d4c258415d3f,

title = "Nano-lithography free formation of high density Ge-on-insulator network for epitaxial template",

abstract = "High-quality Ge-on-insulator (GOI) structures are essential for integrating multi-functional devices onto the Si-platform. We develop the nano-lithography free method for single-crystalline GOI networks by combining partial Ge evaporation and rapid-melting growth techniques. This realizes chip size GOI with high Ge coverage fractions (>75), which is crisscrossed with nano-spacing (∼100 nm width). Over-epitaxy of Ge on the GOI network is also examined, which achieves single-crystalline GOI uniform-plane by covering the nano-spacing. This proves the validity of high-density GOI networks as the epitaxial template. This method will facilitate the heterogeneous integration of Ge, III-V semiconductors, and magnetic materials on the Si-platform.",

author = "Hiroyuki Yokoyama and Kaoru Toko and Taizoh Sadoh and Masanobu Miyao",

note = "Funding Information: A part of this work was supported by Semiconductor Technology Academic Research Center (STARC) and a Grant-in-Aid for Scientific Research from the Ministry of Education, Culture, Sport, Science, and Technology in Japan. The authors wish to thank Dr. I. Mizushima, Dr. N. Tamura, and Dr. M. Yoshimaru of STARC for their helpful discussions in the course of this study.",

year = "2012",

month = feb,

day = "27",

doi = "10.1063/1.3691258",

language = "English",

volume = "100",

journal = "Applied Physics Letters",

issn = "0003-6951",

publisher = "American Institute of Physics Publising LLC",

number = "9",

}

TY - JOUR

T1 - Nano-lithography free formation of high density Ge-on-insulator network for epitaxial template

AU - Yokoyama, Hiroyuki

AU - Toko, Kaoru

AU - Sadoh, Taizoh

AU - Miyao, Masanobu

N1 - Funding Information: A part of this work was supported by Semiconductor Technology Academic Research Center (STARC) and a Grant-in-Aid for Scientific Research from the Ministry of Education, Culture, Sport, Science, and Technology in Japan. The authors wish to thank Dr. I. Mizushima, Dr. N. Tamura, and Dr. M. Yoshimaru of STARC for their helpful discussions in the course of this study.

PY - 2012/2/27

Y1 - 2012/2/27

N2 - High-quality Ge-on-insulator (GOI) structures are essential for integrating multi-functional devices onto the Si-platform. We develop the nano-lithography free method for single-crystalline GOI networks by combining partial Ge evaporation and rapid-melting growth techniques. This realizes chip size GOI with high Ge coverage fractions (>75), which is crisscrossed with nano-spacing (∼100 nm width). Over-epitaxy of Ge on the GOI network is also examined, which achieves single-crystalline GOI uniform-plane by covering the nano-spacing. This proves the validity of high-density GOI networks as the epitaxial template. This method will facilitate the heterogeneous integration of Ge, III-V semiconductors, and magnetic materials on the Si-platform.

AB - High-quality Ge-on-insulator (GOI) structures are essential for integrating multi-functional devices onto the Si-platform. We develop the nano-lithography free method for single-crystalline GOI networks by combining partial Ge evaporation and rapid-melting growth techniques. This realizes chip size GOI with high Ge coverage fractions (>75), which is crisscrossed with nano-spacing (∼100 nm width). Over-epitaxy of Ge on the GOI network is also examined, which achieves single-crystalline GOI uniform-plane by covering the nano-spacing. This proves the validity of high-density GOI networks as the epitaxial template. This method will facilitate the heterogeneous integration of Ge, III-V semiconductors, and magnetic materials on the Si-platform.

UR - http://www.scopus.com/inward/record.url?scp=84857945252&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84857945252&partnerID=8YFLogxK

U2 - 10.1063/1.3691258

DO - 10.1063/1.3691258

M3 - Article

AN - SCOPUS:84857945252

SN - 0003-6951

VL - 100

JO - Applied Physics Letters

JF - Applied Physics Letters

IS - 9

M1 - 092111

ER -

Nano-lithography free formation of high density Ge-on-insulator network for epitaxial template

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this