Multiplier energy reduction through bypassing of partial products

Jun Ni Ohban, V. G. Moshnyaga, K. Inoue

Research output: Chapter in Book/Report/Conference proceedingConference contribution

60 Citations (Scopus)


The design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital multiplier based on dynamic bypassing of partial products. The bypassing elements incorporated into the multiplier hardware eliminate redundant signal transitions, which appear within the carry-save adders when the partial product is zero. Simulations on the real-life DCT data show that the proposed approach can improve power saving of related methods by 12%, while jointly with them, it reduces the power consumption of a 16x16 digital CMOS multiplier by 31%, with 25% area overhead and less than 4% performance degradation in the worst case. The circuit implementation is outlined.

Original languageEnglish
Title of host publicationProceedings - APCCAS 2002
Subtitle of host publicationAsia-Pacific Conference on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages5
ISBN (Electronic)0780376900
Publication statusPublished - 2002
Externally publishedYes
EventAsia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, Indonesia
Duration: Oct 28 2002Oct 31 2002

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS


OtherAsia-Pacific Conference on Circuits and Systems, APCCAS 2002
CityDenpasar, Bali

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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