Memory-CPU size optimization for embedded system designs

Barry Shackleford; Mitsuhiro Yasuda; Etsuko Okushi; Hisao Koizumi; Hiroyuki Tomiyama; Hiroto Yasuura

doi:10.1145/266021.266083

Memory-CPU size optimization for embedded system designs

Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura

Research output: Contribution to journal › Conference article › peer-review

17 Citations (Scopus)

Abstract

Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.

Original language	English
Pages (from-to)	246-251
Number of pages	6
Journal	Proceedings - Design Automation Conference
DOIs	https://doi.org/10.1145/266021.266083
Publication status	Published - 1997
Externally published	Yes
Event	Proceedings of the 1997 34th Design Automation Conference - Anaheim, CA, USA Duration: Jun 9 1997 → Jun 13 1997

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Control and Systems Engineering

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10.1145/266021.266083

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AU - Shackleford, Barry

AU - Yasuda, Mitsuhiro

AU - Okushi, Etsuko

AU - Koizumi, Hisao

AU - Tomiyama, Hiroyuki

AU - Yasuura, Hiroto

PY - 1997

Y1 - 1997

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ER -

Memory-CPU size optimization for embedded system designs

Abstract

All Science Journal Classification (ASJC) codes

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