TY - GEN
T1 - Low-temperature 3D chip-stacking using compliant bump
AU - Watanabe, Naoya
AU - Mori, Takamichi
AU - Asano, Tanemasa
PY - 2008
Y1 - 2008
N2 - We demonstrate low-temperature 3D chip-stacking (number of bumps: 25,200, bump size / bump pitch: 11μm /20 μm, chip-stacking temperature: 30°C) using the compliant bump. Low-temperature 3D chip-stacking was carried out by mechanical caulking using compliant bump and doughnut-shaped electrode. This method is very effective in realizing 3D chip-stacking even at room temperature.
AB - We demonstrate low-temperature 3D chip-stacking (number of bumps: 25,200, bump size / bump pitch: 11μm /20 μm, chip-stacking temperature: 30°C) using the compliant bump. Low-temperature 3D chip-stacking was carried out by mechanical caulking using compliant bump and doughnut-shaped electrode. This method is very effective in realizing 3D chip-stacking even at room temperature.
UR - https://www.scopus.com/pages/publications/63049118006
UR - https://www.scopus.com/pages/publications/63049118006#tab=citedBy
U2 - 10.1109/EPTC.2008.4763466
DO - 10.1109/EPTC.2008.4763466
M3 - Conference contribution
AN - SCOPUS:63049118006
SN - 9781424421183
T3 - 10th Electronics Packaging Technology Conference, EPTC 2008
SP - 393
EP - 398
BT - 10th Electronics Packaging Technology Conference, EPTC 2008
T2 - 10th Electronics Packaging Technology Conference, EPTC 2008
Y2 - 9 December 2008 through 12 December 2008
ER -