Low power and compact desktop ATM PMD

Y. Wakayama, F. Nakano, J. Takeuchi, N. Honda, K. Ishii, T. Sakamoto, T. Fujii

Research output: Contribution to journalConference articlepeer-review


A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 μm CMOS process. Although it contains a UTP 100 m cable equalizer circuit and a clock recovery circuit, a low power 74 mW and a small die area 2.52 mm2 are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized.

Original languageEnglish
Pages (from-to)331-334
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 1997
Externally publishedYes
EventProceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: May 5 1997May 8 1997

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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