Low power and compact desktop ATM PMD

Y. Wakayama; F. Nakano; J. Takeuchi; N. Honda; K. Ishii; T. Sakamoto; T. Fujii

Low power and compact desktop ATM PMD

Y. Wakayama, F. Nakano, J. Takeuchi, N. Honda, K. Ishii, T. Sakamoto, T. Fujii

Research output: Contribution to journal › Conference article › peer-review

Abstract

A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 μm CMOS process. Although it contains a UTP 100 m cable equalizer circuit and a clock recovery circuit, a low power 74 mW and a small die area 2.52 mm² are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized.

Original language	English
Pages (from-to)	331-334
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 1997
Externally published	Yes
Event	Proceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: May 5 1997 → May 8 1997

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

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title = "Low power and compact desktop ATM PMD",

abstract = "A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 μm CMOS process. Although it contains a UTP 100 m cable equalizer circuit and a clock recovery circuit, a low power 74 mW and a small die area 2.52 mm2 are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized.",

author = "Y. Wakayama and F. Nakano and J. Takeuchi and N. Honda and K. Ishii and T. Sakamoto and T. Fujii",

year = "1997",

language = "English",

pages = "331--334",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1997 IEEE Custom Integrated Circuits Conference ; Conference date: 05-05-1997 Through 08-05-1997",

}

TY - JOUR

T1 - Low power and compact desktop ATM PMD

AU - Wakayama, Y.

AU - Nakano, F.

AU - Takeuchi, J.

AU - Honda, N.

AU - Ishii, K.

AU - Sakamoto, T.

AU - Fujii, T.

PY - 1997

Y1 - 1997

N2 - A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 μm CMOS process. Although it contains a UTP 100 m cable equalizer circuit and a clock recovery circuit, a low power 74 mW and a small die area 2.52 mm2 are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized.

AB - A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 μm CMOS process. Although it contains a UTP 100 m cable equalizer circuit and a clock recovery circuit, a low power 74 mW and a small die area 2.52 mm2 are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized.

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UR - http://www.scopus.com/inward/citedby.url?scp=0030681797&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0030681797

SN - 0886-5930

SP - 331

EP - 334

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the 1997 IEEE Custom Integrated Circuits Conference

Y2 - 5 May 1997 through 8 May 1997

ER -

Low power and compact desktop ATM PMD

Abstract

All Science Journal Classification (ASJC) codes

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