A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 μm CMOS process. Although it contains a UTP 100 m cable equalizer circuit and a clock recovery circuit, a low power 74 mW and a small die area 2.52 mm2 are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|Publication status||Published - 1997|
|Event||Proceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA|
Duration: May 5 1997 → May 8 1997
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering