Investigating the common-mode voltage (CMV) is a continuing concern in power electronic inverter, due to the fact that the desired sinusoidal waveforms cannot be obtained from a typical voltage source inverter (VSI). Such difficulty in producing these sinusoidal waveforms is due to the continuous generation of power pulses produced by the pulse width modulation (PWM) strategy applied to the switching devices in inverter legs. In this context, this paper utilizes the interleaved PWM concept for the CMV reduction of paralleled single-stage dc-ac split-source inverters (SSI). Firstly, the conventional SSI structure and basic operation are described and the corresponding CMV waveform is discussed. Then, based on the analysis, the interleaved PWM strategy is proposed in order to restrain the instantaneous CMV peaks, reduce the induced common-mode (CM) leakage current (CMLC), and attenuate the electromagnetic interference (EMI) noise spectra as well. In addition to that, the impact of various interleaved angles is also investigated. Finally, simulation using Simulink models are used to verify the proposed concepts.