Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines

Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

The bandwidth limit between cryogenic and room-temperature environments is a critical bottleneck in superconducting noisy intermediate-scale quantum computers. This paper presents the first trial of algorithm-aware system-level optimization to solve this issue by targeting the quantum approximate optimization algorithm. Our counter-based cryogenic architecture using single-flux quantum logic shows exponential bandwidth reduction and decreases heat inflow and peripheral power consumption of inter-temperature cables, which contributes to the scalability of superconducting quantum computers.

Original languageEnglish
Pages (from-to)6-9
Number of pages4
JournalIEEE Computer Architecture Letters
Volume23
Issue number1
DOIs
Publication statusPublished - Jan 1 2024

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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