Instruction encoding techniques for area minimization of instruction ROM

T. Okuma; H. Tomiyama; A. Inoue; E. Fajar; H. Yasuura

doi:10.1109/isss.1998.730612

Instruction encoding techniques for area minimization of instruction ROM

T. Okuma, H. Tomiyama, A. Inoue, E. Fajar, H. Yasuura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Citations (Scopus)

Abstract

In this paper we propose instruction encoding techniques for embedded system design, which encode immediate fields of instructions to reduce the size of an instruction memory. Although our proposed techniques require an additional decoder for the encoded immediate values, experimental results demonstrate the effectiveness of our techniques to reduce the chip area.

Original language	English
Title of host publication	Proceedings of the 11th International Symposium on System Synthesis, ISSS 1998
Editors	Francky Catthoor
Publisher	IEEE Computer Society
Pages	125-130
Number of pages	6
ISBN (Electronic)	0818686235, 9780818686238
DOIs	https://doi.org/10.1109/isss.1998.730612
Publication status	Published - Dec 2 1998
Externally published	Yes
Event	11th International Symposium on System Synthesis, ISSS 1998 - Hsinchu, Taiwan, Province of China Duration: Dec 2 1998 → Dec 4 1998

Publication series

Name	Proceedings of the International Symposium on System Synthesis
Volume	Part F129250
ISSN (Print)	1080-1820

Other

Other	11th International Symposium on System Synthesis, ISSS 1998
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	12/2/98 → 12/4/98

All Science Journal Classification (ASJC) codes

Hardware and Architecture

Access to Document

10.1109/isss.1998.730612

Cite this

Okuma, T., Tomiyama, H., Inoue, A., Fajar, E., & Yasuura, H. (1998). Instruction encoding techniques for area minimization of instruction ROM. In F. Catthoor (Ed.), Proceedings of the 11th International Symposium on System Synthesis, ISSS 1998 (pp. 125-130). (Proceedings of the International Symposium on System Synthesis; Vol. Part F129250). IEEE Computer Society. https://doi.org/10.1109/isss.1998.730612

Instruction encoding techniques for area minimization of instruction ROM. / Okuma, T.; Tomiyama, H.; Inoue, A. et al.
Proceedings of the 11th International Symposium on System Synthesis, ISSS 1998. ed. / Francky Catthoor. IEEE Computer Society, 1998. p. 125-130 (Proceedings of the International Symposium on System Synthesis; Vol. Part F129250).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Okuma, T, Tomiyama, H, Inoue, A, Fajar, E & Yasuura, H 1998, Instruction encoding techniques for area minimization of instruction ROM. in F Catthoor (ed.), Proceedings of the 11th International Symposium on System Synthesis, ISSS 1998. Proceedings of the International Symposium on System Synthesis, vol. Part F129250, IEEE Computer Society, pp. 125-130, 11th International Symposium on System Synthesis, ISSS 1998, Hsinchu, Taiwan, Province of China, 12/2/98. https://doi.org/10.1109/isss.1998.730612

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author = "T. Okuma and H. Tomiyama and A. Inoue and E. Fajar and H. Yasuura",

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Instruction encoding techniques for area minimization of instruction ROM

Abstract

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All Science Journal Classification (ASJC) codes

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