Improved gain 60GHz CMOS antenna with N-well grid

Adel Barakat, Ahmed Allam, Hala Elsadek, Adel B. Abdel-Rahman, Ramesh K. Pokharel, Takana Kaho

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


This paper presents a novel technique to enhance Antenna-on- Chip gain by introducing a high resistivity layer below it. Instead of using the costly ion implantation method to increase resistivity, the N-well that is available in the standard CMOS process is used. A distributed grid structure of N-well on P-type substrate is designed such that the P and N semiconductors types are fully depleted forming a layer with high resistivity. By an electromagnetic simulation, the using depletion layers enhance the antenna gain and radiation efficiency without increasing the occupied area. The simulated and measured |S11| are in fair agreement. The measured gain is −1.5 dBi at 66 GHz.

Original languageEnglish
Article number20151115
JournalIEICE Electronics Express
Issue number5
Publication statusPublished - Feb 19 2016

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering


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