TY - GEN
T1 - High Switching Controllability Trench Gate Design in Si-IGBTs
AU - Saito, Wataru
AU - Nishizawa, Shin Ichi
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/9
Y1 - 2020/9
N2 - A new trench gate design in Si-IGBTs is proposed and analyzed for high controllability of turn-off dV/dt and turn-on dI/dt with low loss operation. Power electronics systems require not only low power loss but also low EMI noise for high cost performance by system downsizing. Although turn-off loss $E _{off}$ and on-state voltage drop $V _ce(sat)$trade-off of IGBT can be improved by enhancement of Injection Enhancement (IE) effect, $E _off$ is limited by dynamic avalanche at low external gate resistance $R_{g}$ condition. In addition, EMI noise is induced by negative gate capacitance at the turn-on switching due to high dI/dt and large surge current $I_{surge}$. Therefore, the system designers require good switching controllability by $R_{g}$ to adjust the power loss and EMI noise trade-off for the optimum system design. This paper shows the dynamic avalanche and negative gate capacitance can be suppressed by management of electric field concentration and hole current flow around the trench gate by proposed Alternated Trench (AT) structure and both good switching controllability and low power loss can be obtained.
AB - A new trench gate design in Si-IGBTs is proposed and analyzed for high controllability of turn-off dV/dt and turn-on dI/dt with low loss operation. Power electronics systems require not only low power loss but also low EMI noise for high cost performance by system downsizing. Although turn-off loss $E _{off}$ and on-state voltage drop $V _ce(sat)$trade-off of IGBT can be improved by enhancement of Injection Enhancement (IE) effect, $E _off$ is limited by dynamic avalanche at low external gate resistance $R_{g}$ condition. In addition, EMI noise is induced by negative gate capacitance at the turn-on switching due to high dI/dt and large surge current $I_{surge}$. Therefore, the system designers require good switching controllability by $R_{g}$ to adjust the power loss and EMI noise trade-off for the optimum system design. This paper shows the dynamic avalanche and negative gate capacitance can be suppressed by management of electric field concentration and hole current flow around the trench gate by proposed Alternated Trench (AT) structure and both good switching controllability and low power loss can be obtained.
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U2 - 10.1109/ISPSD46842.2020.9170118
DO - 10.1109/ISPSD46842.2020.9170118
M3 - Conference contribution
AN - SCOPUS:85090567507
T3 - Proceedings of the International Symposium on Power Semiconductor Devices and ICs
SP - 447
EP - 450
BT - Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020
Y2 - 13 September 2020 through 18 September 2020
ER -