TY - JOUR
T1 - High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology
AU - Galal, A. I.A.
AU - Pokharel, R.
AU - Kanaya, H.
AU - Yoshida, K.
N1 - Funding Information:
In April 2005, he joined the Department of Electronics, Graduate School of Information Science and Electrical Engineering, Kyushu University where he is currently an assistant professor. His current research interests include the employment of passive components such as CPW in RF CMOS system LSI, EMC and signal integrity issues of LSI, and low-noise and high linear RF front-end architectures. He is a member of the IEEE. Dr. Pokharel was a recipient of the Monbu-Kagakusho Scholarship of the Japanese Government (1997–2003) and an excellent COE research presentation award from the University of Tokyo in 2003.
Funding Information:
This work was partly supported by a grant of Regional Innovation Cluster Program (Global Type 2nd Stage) from the Ministry of Education, Culture, Sports, Science and Technology (MEXT) and a Grant-in-Aid for Scientific Research from JSPS (KAKENHI). This work was also partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with CADENCE Corporation and Agilent Corporation and thanks the Egyptian Government for supporting this scholarship.
PY - 2012/1
Y1 - 2012/1
N2 - A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm2, including all pads. The measured input return loss is kept below -11 dB, and the output return loss is -8 dB, from 3.1 to 10.6 GHz.
AB - A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm2, including all pads. The measured input return loss is kept below -11 dB, and the output return loss is -8 dB, from 3.1 to 10.6 GHz.
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U2 - 10.1016/j.aeue.2011.04.010
DO - 10.1016/j.aeue.2011.04.010
M3 - Article
AN - SCOPUS:81155134672
SN - 1434-8411
VL - 66
SP - 12
EP - 17
JO - AEU - International Journal of Electronics and Communications
JF - AEU - International Journal of Electronics and Communications
IS - 1
ER -