TY - JOUR
T1 - High efficiency, good linearity, and excellent phase linearity of 3.1-4.8 GHz CMOS UWB PA with a current-reused technique
AU - Murad, S. A.Z.
AU - Pokharel, R. K.
AU - Sapawi, R.
AU - Kanaya, H.
AU - Yoshida, K.
N1 - Funding Information:
The authors would like to thanks Ministry of Higher Education Malaysia (KPT) and University Malaysia Perlis (UniMAP) for the financial support to pursue the PhD degree work.
Funding Information:
This work was partly supported by a grant of Ministry of Education, Culture, Sports, Science and Technology (MEXT) and KAKENHI. This work was also partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with CADENCE Corporation and Agilent Corporation.
PY - 2010/8
Y1 - 2010/8
N2 - This paper describes the design of 3.1 to 4.8 GHz CMOS power amplifier (PA) for ultra-wideband (UWB) applications using 0.18-m CMOS technology. The UWB PA proposed here employs cascode topology with a currentreused technique to enhance the gain at the upper end of the desired band, an inter-stage inductor, and a resistive feedback at the second stage to obtain the flatness gain. The measurement results indicated that the input return loss (S11) was less than -5 dB, output return loss (S22) was less than -8 dB, and average power gain of 10.3 dB with a flatness about 0.8 dB. The input 1 dB compression point about -2 dBm and excellent phase linearity (group delay) of ± 135 ps across the whole band were obtained. Moreover, a very high power added efficiency (PAE) of 40.5% at 4 GHz with 50Σ load impedance was achieved with a power consumption of 24- mW.
AB - This paper describes the design of 3.1 to 4.8 GHz CMOS power amplifier (PA) for ultra-wideband (UWB) applications using 0.18-m CMOS technology. The UWB PA proposed here employs cascode topology with a currentreused technique to enhance the gain at the upper end of the desired band, an inter-stage inductor, and a resistive feedback at the second stage to obtain the flatness gain. The measurement results indicated that the input return loss (S11) was less than -5 dB, output return loss (S22) was less than -8 dB, and average power gain of 10.3 dB with a flatness about 0.8 dB. The input 1 dB compression point about -2 dBm and excellent phase linearity (group delay) of ± 135 ps across the whole band were obtained. Moreover, a very high power added efficiency (PAE) of 40.5% at 4 GHz with 50Σ load impedance was achieved with a power consumption of 24- mW.
UR - http://www.scopus.com/inward/record.url?scp=78149239855&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78149239855&partnerID=8YFLogxK
U2 - 10.1109/TCE.2010.5606253
DO - 10.1109/TCE.2010.5606253
M3 - Article
AN - SCOPUS:78149239855
SN - 0098-3063
VL - 56
SP - 1241
EP - 1246
JO - IEEE Transactions on Consumer Electronics
JF - IEEE Transactions on Consumer Electronics
IS - 3
M1 - 5606253
ER -