TY - JOUR
T1 - High-Efficiency CMOS RF-to-DC Rectifier Based on Dynamic Threshold Reduction Technique for Wireless Charging Applications
AU - Mohamed, Manal M.
AU - Fahmy, Ghazal A.
AU - Abdel-Rahman, Adel B.
AU - Allam, Ahmed
AU - Barakat, Adel
AU - Abo-Zahhad, Mohammed
AU - Jia, Hongting
AU - Pokharel, Ramesh K.
N1 - Funding Information:
This work was supported in part by the Education Center (VDEC) at the University of Tokyo in collaboration with the Cadence and Keysight Corporation, in part by the Egyptian Ministry of Higher Education (MoHE), Cairo, Egypt, and in part by the Egypt–Japan University of Science and Technology (EJUST), Alexandria, Egypt.
Funding Information:
This work was supported in part by the Education Center (VDEC) at the University of Tokyo in collaboration with the Cadence and Keysight Corporation, in part by the Egyptian Ministry of Higher Education (MoHE), Cairo, Egypt, and in part by the Egypt-Japan University of Science and Technology (EJUST), Alexandria, Egypt.
Publisher Copyright:
© 2013 IEEE.
PY - 2018/8/21
Y1 - 2018/8/21
N2 - This paper presents a high-efficiency CMOS rectifier based on an improved dynamic threshold reduction technique (DTR). The proposed DTR consists of a clamper circuit that biases the gates of pMOS diode switches through a capacitor and diode-connected pMOS transistor. The clamper is used to insert a negative dc level to the input RF signal; therefore, more negative RF signal can be obtained to bias the gates of the main rectifying pMOS devices during its conduction phase. This mechanism reduces the threshold voltage of the main pMOS transistors and increases their sensitivity to the RF input signal. The proposed rectifier is implemented in a 0.18-μm CMOS technology and tested. The measurement shows a peak power conversion efficiency of 86% and an output voltage of 0.52 V at an input power of-16.5 dBm and an input frequency of 402 MHz. The core area of chip excluding measurement pads is 0.024
AB - This paper presents a high-efficiency CMOS rectifier based on an improved dynamic threshold reduction technique (DTR). The proposed DTR consists of a clamper circuit that biases the gates of pMOS diode switches through a capacitor and diode-connected pMOS transistor. The clamper is used to insert a negative dc level to the input RF signal; therefore, more negative RF signal can be obtained to bias the gates of the main rectifying pMOS devices during its conduction phase. This mechanism reduces the threshold voltage of the main pMOS transistors and increases their sensitivity to the RF input signal. The proposed rectifier is implemented in a 0.18-μm CMOS technology and tested. The measurement shows a peak power conversion efficiency of 86% and an output voltage of 0.52 V at an input power of-16.5 dBm and an input frequency of 402 MHz. The core area of chip excluding measurement pads is 0.024
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U2 - 10.1109/ACCESS.2018.2866457
DO - 10.1109/ACCESS.2018.2866457
M3 - Article
AN - SCOPUS:85052715787
SN - 2169-3536
VL - 6
SP - 46826
EP - 46832
JO - IEEE Access
JF - IEEE Access
M1 - 8443341
ER -