TY - JOUR
T1 - High Efficiency and Small Group Delay Variations 0.18-μ m CMOS UWB Power Amplifier
AU - Mosalam, Hamed
AU - Allam, A.
AU - Jia, Hongting
AU - Abdel-Rahman, A. B.
AU - Pokharel, Ramesh K.
N1 - Funding Information:
Manuscript received July 2, 2018; accepted August 30, 2018. Date of publication September 13, 2018; date of current version March 26, 2019. This work was supported in part by the Grant-in-Aid for Scientific Research under Grant JP 16K06301, in part by VLSI Design and Education Center, in part by the University of Tokyo in collaboration with Cadence and Keysight Corporations, in part by the Egyptian Ministry of Higher Education, Cairo, Egypt, and in part by the Egypt-Japan University of Science and Technology, Alexandria, Egypt. This brief was recommended by Associate Editor V. Saxena. (Corresponding author: Hamed Mosalam.) H. Mosalam is with the Egypt-Japan University of Science and Technology, Alexandria 21934, Egypt, and also with Microelectronics Department, Electronics Research Institute, Giza 12622, Egypt (e-mail: hamed.mosalam@eri.sci.eg).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2019/4
Y1 - 2019/4
N2 - A new staggered tuning technique, by optimizing the inter-stage matching circuit, is proposed to realize a power amplifier (PA) with small group delay (GD) variations and excellent gain flatness across the full bandwidth of ultra-wideband (UWB) system. The proposed PA consists of two stages where the first stage is constructed by a current-reuse with shunt RC feedback topology to realize gain flatness and low power consumption. The design is implemented in 0.18 μ m commentary metal-oxide semiconductor (CMOS) technology, fabricated, and tested. The proposed PA has a measured power gain (|S21|) of 11.5 ± 0.7 dB, maximum power-added efficiency (PAE) of 26% and an output 1-dB compression point of 9 dBm, respectively, and this is the maximum PAE among CMOS PAs that cover the full bandwidth of UWB system. Besides, the PA has a small GD variations of ± 68 ps which is the lowest till date.
AB - A new staggered tuning technique, by optimizing the inter-stage matching circuit, is proposed to realize a power amplifier (PA) with small group delay (GD) variations and excellent gain flatness across the full bandwidth of ultra-wideband (UWB) system. The proposed PA consists of two stages where the first stage is constructed by a current-reuse with shunt RC feedback topology to realize gain flatness and low power consumption. The design is implemented in 0.18 μ m commentary metal-oxide semiconductor (CMOS) technology, fabricated, and tested. The proposed PA has a measured power gain (|S21|) of 11.5 ± 0.7 dB, maximum power-added efficiency (PAE) of 26% and an output 1-dB compression point of 9 dBm, respectively, and this is the maximum PAE among CMOS PAs that cover the full bandwidth of UWB system. Besides, the PA has a small GD variations of ± 68 ps which is the lowest till date.
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U2 - 10.1109/TCSII.2018.2870165
DO - 10.1109/TCSII.2018.2870165
M3 - Article
AN - SCOPUS:85053294583
SN - 1549-7747
VL - 66
SP - 592
EP - 596
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 4
M1 - 8464178
ER -