High-density room-temperature 3D chip-stacking using mechanical caulking with compliant bump and through-hole-electrode

Naoya Watanabe; Michihiro Kawashita; Yasuhiro Yoshimura; Naotaka Tanaka; Tanemasa Asano

doi:10.1115/InterPACK2009-89274

High-density room-temperature 3D chip-stacking using mechanical caulking with compliant bump and through-hole-electrode

Naoya Watanabe, Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Tanemasa Asano

Integrated Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this study, we employ a novel compliant bump in 3D chip-stacking using mechanical caulking. The compliant bump prepared in this work has a cone-like structure and is made of. Au. It is fabricated using an "undercut resist method," which combines undercut resist pattern formation with electroplating. The size of the compliant bump (approximately 10-30 μm in diameter) is much smaller than that of the stud bump. We demonstrate that by using a mechanical caulking process with a compliant bump and a through-hole-electrode, high-density through-hole-electrode interconnection (I/O number: 8,000, pitch: 20 μm) becomes possible, even at room temperature.

Original language	English
Title of host publication	Proceedings of the ASME InterPack Conference 2009, IPACK2009
Pages	33-38
Number of pages	6
DOIs	https://doi.org/10.1115/InterPACK2009-89274
Publication status	Published - 2010
Event	2009 ASME InterPack Conference, IPACK2009 - San Francisco, CA, United States Duration: Jul 19 2009 → Jul 23 2009

Publication series

Name	Proceedings of the ASME InterPack Conference 2009, IPACK2009
Volume	1

Other

Other	2009 ASME InterPack Conference, IPACK2009
Country/Territory	United States
City	San Francisco, CA
Period	7/19/09 → 7/23/09

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1115/InterPACK2009-89274

Cite this

Watanabe, N., Kawashita, M., Yoshimura, Y., Tanaka, N., & Asano, T. (2010). High-density room-temperature 3D chip-stacking using mechanical caulking with compliant bump and through-hole-electrode. In Proceedings of the ASME InterPack Conference 2009, IPACK2009 (pp. 33-38). (Proceedings of the ASME InterPack Conference 2009, IPACK2009; Vol. 1). https://doi.org/10.1115/InterPACK2009-89274

High-density room-temperature 3D chip-stacking using mechanical caulking with compliant bump and through-hole-electrode. / Watanabe, Naoya; Kawashita, Michihiro; Yoshimura, Yasuhiro et al.
Proceedings of the ASME InterPack Conference 2009, IPACK2009. 2010. p. 33-38 (Proceedings of the ASME InterPack Conference 2009, IPACK2009; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Watanabe, N, Kawashita, M, Yoshimura, Y, Tanaka, N & Asano, T 2010, High-density room-temperature 3D chip-stacking using mechanical caulking with compliant bump and through-hole-electrode. in Proceedings of the ASME InterPack Conference 2009, IPACK2009. Proceedings of the ASME InterPack Conference 2009, IPACK2009, vol. 1, pp. 33-38, 2009 ASME InterPack Conference, IPACK2009, San Francisco, CA, United States, 7/19/09. https://doi.org/10.1115/InterPACK2009-89274

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High-density room-temperature 3D chip-stacking using mechanical caulking with compliant bump and through-hole-electrode

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