Gate drive circuit for current balancing of parallel-connected SiC-JFETs under avalanche mode

Taro Takamori; Keiji Wada; Wataru Saito; Shin ichi Nishizawa

doi:10.1016/j.microrel.2020.113776

Gate drive circuit for current balancing of parallel-connected SiC-JFETs under avalanche mode

Taro Takamori, Keiji Wada, Wataru Saito, Shin ichi Nishizawa

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

This paper proposes a gate drive circuit for the current balancing of parallel-connected SiC-JFETs under avalanche mode. For a solid-state DC circuit breaker, the power devices have to be connected in parallel to reduce the ON-resistance and increase the current rating. In addition, it is reported that the SiC-JFET is suitable power devices from the viewpoint of both conduction loss and long-term reliability. This paper presents the behavior of current balancing of SiC-JFETs in parallel, and then proposes a design procedure of gate drive circuits. The gate drive circuits can achieve the current balance equalization of parallel-connected SiC-JFETs under avalanche mode. The validity of the proposed gate drive circuit is verified by the experiment that uses 1.2 kV SiC-JFETs in a 400 V system.

Original language	English
Article number	113776
Journal	Microelectronics Reliability
Volume	114
DOIs	https://doi.org/10.1016/j.microrel.2020.113776
Publication status	Published - Nov 2020

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Safety, Risk, Reliability and Quality
Surfaces, Coatings and Films
Atomic and Molecular Physics, and Optics
Electrical and Electronic Engineering

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10.1016/j.microrel.2020.113776

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title = "Gate drive circuit for current balancing of parallel-connected SiC-JFETs under avalanche mode",

abstract = "This paper proposes a gate drive circuit for the current balancing of parallel-connected SiC-JFETs under avalanche mode. For a solid-state DC circuit breaker, the power devices have to be connected in parallel to reduce the ON-resistance and increase the current rating. In addition, it is reported that the SiC-JFET is suitable power devices from the viewpoint of both conduction loss and long-term reliability. This paper presents the behavior of current balancing of SiC-JFETs in parallel, and then proposes a design procedure of gate drive circuits. The gate drive circuits can achieve the current balance equalization of parallel-connected SiC-JFETs under avalanche mode. The validity of the proposed gate drive circuit is verified by the experiment that uses 1.2 kV SiC-JFETs in a 400 V system.",

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AU - Takamori, Taro

AU - Wada, Keiji

AU - Saito, Wataru

AU - Nishizawa, Shin ichi

PY - 2020/11

Y1 - 2020/11

N2 - This paper proposes a gate drive circuit for the current balancing of parallel-connected SiC-JFETs under avalanche mode. For a solid-state DC circuit breaker, the power devices have to be connected in parallel to reduce the ON-resistance and increase the current rating. In addition, it is reported that the SiC-JFET is suitable power devices from the viewpoint of both conduction loss and long-term reliability. This paper presents the behavior of current balancing of SiC-JFETs in parallel, and then proposes a design procedure of gate drive circuits. The gate drive circuits can achieve the current balance equalization of parallel-connected SiC-JFETs under avalanche mode. The validity of the proposed gate drive circuit is verified by the experiment that uses 1.2 kV SiC-JFETs in a 400 V system.

AB - This paper proposes a gate drive circuit for the current balancing of parallel-connected SiC-JFETs under avalanche mode. For a solid-state DC circuit breaker, the power devices have to be connected in parallel to reduce the ON-resistance and increase the current rating. In addition, it is reported that the SiC-JFET is suitable power devices from the viewpoint of both conduction loss and long-term reliability. This paper presents the behavior of current balancing of SiC-JFETs in parallel, and then proposes a design procedure of gate drive circuits. The gate drive circuits can achieve the current balance equalization of parallel-connected SiC-JFETs under avalanche mode. The validity of the proposed gate drive circuit is verified by the experiment that uses 1.2 kV SiC-JFETs in a 400 V system.

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Gate drive circuit for current balancing of parallel-connected SiC-JFETs under avalanche mode

Abstract

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