Fpga-based lifting wavelet processor for real-time signal detection

Koichi Kuzume, Koichi Niijima, Shigeru Takano

    Research output: Contribution to journalArticlepeer-review

    25 Citations (Scopus)


    This paper presents the realization of a lifting wavelet processor for signal detection on a field programmable gate array (FPGA) device. This processor implements an algorithm for detecting target portions from a signal using an integer type Haar lifting wavelet transform (IHLWT), which we proposed. Since our detection algorithm is very simple because of short filter length in the IHLWT, the VLSI can be designed using a small amount of circuitry, consisting of only 6 multipliers and 9 adders. Therefore, it can realize the high-speed detection of target signals by constructing a pipeline architecture. The VLSI is designed using hardware description language (HDL) and is simulated on the FPGA in practice. The completed prototype is tested through software-generated signals and utility-sampled signals, in which test scenarios covering several kinds of electrocardiogram (ECG) signals are examined thoroughly. From the results, it is confirmed that the proposed processor can execute target signal detection from the measured ECG signals in real time.

    Original languageEnglish
    Pages (from-to)1931-1940
    Number of pages10
    JournalSignal Processing
    Issue number10
    Publication statusPublished - Oct 2004

    All Science Journal Classification (ASJC) codes

    • Control and Systems Engineering
    • Software
    • Signal Processing
    • Computer Vision and Pattern Recognition
    • Electrical and Electronic Engineering


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