FPGA and ASIC implementations of the ηT pairing in characteristic three

Jean Luc Beuchat; Hiroshi Doi; Kaoru Fujita; Atsuo Inomata; Piseth Ith; Akira Kanaoka; Masayoshi Katouno; Masahiro Mambo; Eiji Okamoto; Takeshi Okamoto; Takaaki Shiga; Masaaki Shirase; Ryuji Soga; Tsuyoshi Takagi; Ananda Vithanage; Hiroyasu Yamamoto

doi:10.1016/j.compeleceng.2009.05.001

FPGA and ASIC implementations of the η_T pairing in characteristic three

Jean Luc Beuchat, Hiroshi Doi, Kaoru Fujita, Atsuo Inomata, Piseth Ith, Akira Kanaoka, Masayoshi Katouno, Masahiro Mambo, Eiji Okamoto, Takeshi Okamoto, Takaaki Shiga, Masaaki Shirase, Ryuji Soga, Tsuyoshi Takagi, Ananda Vithanage, Hiroyasu Yamamoto

Laboratory of Mathematical Design for Advanced Cryptography

Research output: Contribution to journal › Article › peer-review

13 Citations (Scopus)

Abstract

Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. As they rely critically on efficient implementations of pairing primitives, the study of hardware accelerators has become an active research area. In this paper, we propose two coprocessors for the reduced η_T pairing introduced by Barreto et al. as an alternative means of computing the Tate pairing on supersingular elliptic curves. We prototyped our architectures on FPGAs. According to our place-and-route results, our coprocessors compare favorably with other solutions described in the open literature. We eventually present the first ASIC implementation of the reduced η_T pairing.

Original language	English
Pages (from-to)	73-87
Number of pages	15
Journal	Computers and Electrical Engineering
Volume	36
Issue number	1
DOIs	https://doi.org/10.1016/j.compeleceng.2009.05.001
Publication status	Published - Jan 2010

All Science Journal Classification (ASJC) codes

Control and Systems Engineering
Computer Science(all)
Electrical and Electronic Engineering

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10.1016/j.compeleceng.2009.05.001

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Beuchat, J. L., Doi, H., Fujita, K., Inomata, A., Ith, P., Kanaoka, A., Katouno, M., Mambo, M., Okamoto, E., Okamoto, T., Shiga, T., Shirase, M., Soga, R., Takagi, T., Vithanage, A., & Yamamoto, H. (2010). FPGA and ASIC implementations of the η_T pairing in characteristic three. Computers and Electrical Engineering, 36(1), 73-87. https://doi.org/10.1016/j.compeleceng.2009.05.001

Beuchat, JL, Doi, H, Fujita, K, Inomata, A, Ith, P, Kanaoka, A, Katouno, M, Mambo, M, Okamoto, E, Okamoto, T, Shiga, T, Shirase, M, Soga, R, Takagi, T, Vithanage, A & Yamamoto, H 2010, 'FPGA and ASIC implementations of the η_T pairing in characteristic three', Computers and Electrical Engineering, vol. 36, no. 1, pp. 73-87. https://doi.org/10.1016/j.compeleceng.2009.05.001

@article{092d00d1e6d74aa18bb7af5ae07cc301,

title = "FPGA and ASIC implementations of the ηT pairing in characteristic three",

abstract = "Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. As they rely critically on efficient implementations of pairing primitives, the study of hardware accelerators has become an active research area. In this paper, we propose two coprocessors for the reduced ηT pairing introduced by Barreto et al. as an alternative means of computing the Tate pairing on supersingular elliptic curves. We prototyped our architectures on FPGAs. According to our place-and-route results, our coprocessors compare favorably with other solutions described in the open literature. We eventually present the first ASIC implementation of the reduced ηT pairing.",

author = "Beuchat, {Jean Luc} and Hiroshi Doi and Kaoru Fujita and Atsuo Inomata and Piseth Ith and Akira Kanaoka and Masayoshi Katouno and Masahiro Mambo and Eiji Okamoto and Takeshi Okamoto and Takaaki Shiga and Masaaki Shirase and Ryuji Soga and Tsuyoshi Takagi and Ananda Vithanage and Hiroyasu Yamamoto",

note = "Funding Information: The authors thank the anonymous referees for their valuable comments. This work was supported by the New Energy and Industrial Technology Development Organization (NEDO), Japan. ",

year = "2010",

month = jan,

doi = "10.1016/j.compeleceng.2009.05.001",

language = "English",

volume = "36",

pages = "73--87",

journal = "Computers and Electrical Engineering",

issn = "0045-7906",

publisher = "Elsevier Limited",

number = "1",

}

TY - JOUR

T1 - FPGA and ASIC implementations of the ηT pairing in characteristic three

AU - Beuchat, Jean Luc

AU - Doi, Hiroshi

AU - Fujita, Kaoru

AU - Inomata, Atsuo

AU - Ith, Piseth

AU - Kanaoka, Akira

AU - Katouno, Masayoshi

AU - Mambo, Masahiro

AU - Okamoto, Eiji

AU - Okamoto, Takeshi

AU - Shiga, Takaaki

AU - Shirase, Masaaki

AU - Soga, Ryuji

AU - Takagi, Tsuyoshi

AU - Vithanage, Ananda

AU - Yamamoto, Hiroyasu

N1 - Funding Information: The authors thank the anonymous referees for their valuable comments. This work was supported by the New Energy and Industrial Technology Development Organization (NEDO), Japan.

PY - 2010/1

Y1 - 2010/1

N2 - Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. As they rely critically on efficient implementations of pairing primitives, the study of hardware accelerators has become an active research area. In this paper, we propose two coprocessors for the reduced ηT pairing introduced by Barreto et al. as an alternative means of computing the Tate pairing on supersingular elliptic curves. We prototyped our architectures on FPGAs. According to our place-and-route results, our coprocessors compare favorably with other solutions described in the open literature. We eventually present the first ASIC implementation of the reduced ηT pairing.

AB - Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. As they rely critically on efficient implementations of pairing primitives, the study of hardware accelerators has become an active research area. In this paper, we propose two coprocessors for the reduced ηT pairing introduced by Barreto et al. as an alternative means of computing the Tate pairing on supersingular elliptic curves. We prototyped our architectures on FPGAs. According to our place-and-route results, our coprocessors compare favorably with other solutions described in the open literature. We eventually present the first ASIC implementation of the reduced ηT pairing.

UR - http://www.scopus.com/inward/record.url?scp=72449191229&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=72449191229&partnerID=8YFLogxK

U2 - 10.1016/j.compeleceng.2009.05.001

DO - 10.1016/j.compeleceng.2009.05.001

M3 - Article

AN - SCOPUS:72449191229

SN - 0045-7906

VL - 36

SP - 73

EP - 87

JO - Computers and Electrical Engineering

JF - Computers and Electrical Engineering

IS - 1

ER -

FPGA and ASIC implementations of the η_T pairing in characteristic three

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